Microprocessor designs routinely allow a bus to have multiple masters through a defined bus arbitration scheme. Typically, an external device will request ownership of the bus via a bus request signal. The external device is granted ownership by the arbitration block with the assertion of the bus grant output. Typically, the arbitration block is integrated on the same device as the microprocessor core. When the bus arbitration block grants the bus to an external master, the CPU cores are quickly stalled. When the cores are stalled, any power consumed by the core, and more specifically, by the core's clock tree is unnecessarily wasted. Therefore it would be desirable to implement a microprocessor with a bus arbitration block that eliminated unnecessary power consumption in the CPU core when an alternate bus master has been granted control of the system bus by the arbitration block. In addition, microprocessor designs typically accommodate a low power state and a debug state in addition to a normal operating state. In a conventional design, bus arbitration is prohibited when the processor is in either the debug state or the low power state. Therefore, it would be further desirable to implement a processor in which arbitration of the system bus could be accommodated independent of the operating state of the processor.
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